3D XPoint has a lot to chew on. There hasn’t been an announcement this big in the memory industry since the invention of NAND in 1989 and while DRAM and NAND have improved and scaled a lot over the decades, 3D XPoint is really a new class of memory. It’s fast, durable, scalable and non-volatile, whereas DRAM and NAND each only meet two of these criteria. It fills the niche between DRAM and NAND by taking the best characteristics of both technologies and creating a memory unlike anything we have seen before.
This is a bonafide game changer. DRAM which has nanosecond latency, this new NVRAM (non-volatile-RAM) has latency in the 10’s of nano second range.
So how could this affect database engines and CPU technologies ?.
The Database Engine
For a long time database engines have been designed on the assumption that primary storage is many orders of magnitude slower that main memory, it is for this very reason that:
- Write behind behaviour exists (checkpoints)
- Read ahead behaviour exists
- Compression exists, so that we can increase the effective bandwidth of the storage and put to good use those CPU cores which might otherwise be under utilised
Think of a world in which primary storage is virtually as fast as main memory, how do you use this ?, as storage or does this disappear and you treat the NVRAM as one great big buffer pool with persistance ?. Page life expectancy as a concept becomes irrelevant as does the need to defragment indexes. A lot of DBA performance tuning lore is turned on its head, the general rule of thumb is that most database systems are IO bound, most could now become CPU bound. At this juncture a SAN or storage admin might not be the best place to be career wise. No one knows how this will be priced or even deployed in machines, but we are on the cusp of the next major inflection point n the world of memory and storage, aside from the artcile’s wrap-up comments quoted at the top of this post, the next biggest takeaway is this:
Meanwhile unlike many next generation memory technologies out there at the moment, 3D XPoint is the furthest along and doesn’t only exist on paper or in a lab. Intel and Micron are currently sampling the first generation die that is being produced at the companies’ jointly owned fab in Lehi, Utah.
The End Game
This new non-volatile memory is close to having the same performance characteristics as DRAM, but its not quite there yet, the latency is still a 10th of a nano second slower. The end game is the development of NVRAM technologies which match or exceed DRAM performance. What one of the main ideas behind The Machine, a project by HP, is to collapse the memory and stoage hierarchy by memory and mass storage becoming one of the same. The anandtech artcile states that 3D XPoint memory is not being pitched as a like for like replacement for main memory:
First and foremost, Intel and Micron are making it clear that they are not positioning 3D XPoint as a replacement technology for either NAND or DRAM, and in that scale it has been talked about more in its applications nearer NAND than DRAM. It’s supposed to complement both and provide a technology that sits in between the two by filling the latency and cost gap exists between DRAM and NAND. Basically, 3D XPoint is a new tier in the computer architecture because it can be used as either slower, non-volitile memory or much faster storage.
However, there is no doubt that we are knocking on the door of memory technologies that are DRAM like in performance but with durability, this raises a number of interesting questions and opportunities which I will cover in the rest of this post.
Compare and Swap
In computer science, compare-and-swap (CAS) is an atomic instruction used in multithreading to achieve synchronization. It compares the contents of a memory location to a given value and, only if they are the same, modifies the contents of that memory location to a given new value. This is done as a single atomic operation. The atomicity guarantees that the new value is calculated based on up-to-date information; if the value had been updated by another thread in the meantime, the write would fail. The result of the operation must indicate whether it performed the substitution; this can be done either with a simple boolean response (this variant is often called compare-and-set), or by returning the value read from the memory location (not the value written to it).
The use of compare-and-swap primitives underpins the lock and latch free nature of Hekaton, if an NVRAM can be produced that matches the performance characteristics of main memory and has a greater density, x10 according to the Anandtech artcile, could Hekaton become the database engine that is used by default ?. “In memory” is important because as soon as a table spills out of this, compare-and-swap cannot be used, hence our in-memory table uses the legacy database engine.
Do We Still Need Memory ?
Yes, because there is still a big latency penalty to be paid whenever we go off the CPU socket and out to main memory:
If We Require A New Form Of Memory, What Will It Look Like ?
I think hybrid memory cube technology will replace main memory or be used as a 4th level CPU cache. Will This Change CPU Technology ?
Modern Intel processors consume data from memory and the PCIe bus via the “Root complex”, the idea behind this is that it removes the need to have chips that provide memory bus / PCIe bus bridging. How do we get data from this new NVRAM into the CPU ?, do we stick it on a PCIe card, place it on DIMM sticks . . . or is a complete rethink required, is a new bus and root complex architecture required for this ?. Is this going to usher in a new class of hyper-converged systems ?. If the new generation of NVRAM is treated as memory, data can be persisted and read without incurring any of the interrupt service requests usually generated by devices using the PCIe bus:
To quote Bob Dylan: The Times They Are A Changin’ . . . .